The present invention relates to a lock-detection circuit and a phase-locked-loop (PLL) circuit, and particularly relates to a lock-detection circuit configured to detect the phase synchronization between a reference signal and an oscillation-output signal transmitted from a voltage-controlled-oscillation circuit, and a PLL circuit including the lock-detection circuit.
A known and typical PLL circuit 40 includes a phase-frequency-detection (PFD) circuit 41, a charge pump (CP) 42, a loop filter (LF) 43, and a voltage-controlled-oscillation (VCO) circuit 44, as shown in FIG. 6. A reference signal REFCLK is externally transmitted to the PLL circuit 40 and the phase-and-frequency difference between the reference signal REFCLK and an oscillation-output signal FBCLK transmitted from the voltage-controlled-oscillation circuit 44 is detected by the phase-frequency-detection circuit 41. The phase-frequency-detection circuit 41 transmits the up-pulse signal UP and down-pulse signal DOWN corresponding to the phase-and-frequency difference to the charge pump 42. Here, the charge pump 42 operates with a negative logic. Therefore, when the phase of the reference signal REFCLK synchronizes with that of the oscillation-output signal FBCLK, each of the up-pulse signal UP and the down-pulse signal DOWN remains in a “H” state, and an output signal CPOUT is not transmitted from the charge pump 42. If the phase of the oscillation-output signal FBCLK delays with reference to that of the reference signal RFCLK, an up-pulse signal UP having the “L” pulse width corresponding to the phase difference between the reference signal REFCLK and the oscillation-output signal FBCLK is externally transmitted. Here, the down-pulse signal DOWN remains in a “H” state. If the phase of the oscillation-output signal FBCLK advances with reference to that of the reference signal REFCLK, a down-pulse signal DOWN having the “L” pulse width corresponding to the phase difference between the reference signal REFCLK and the oscillation-output signal FBCLK is externally transmitted. Here, the up-pulse signal UP remains in a “H” state. The charge pump 42 electrically charges and/or discharges the loop filter 43 according to the “L” pulse width of up-pulse signal UP and the down-pulse signal DOWN that are transmitted from the phase-frequency-detection circuit 41. A control signal VCONT determined by electrical charges accumulated in the capacitor of the loop filter 43 is transmitted to the voltage-controlled-oscillation circuit 44 and the voltage-controlled-oscillation circuit 44 transmits an oscillation-output signal FBCLK with the frequency corresponding to the voltage of the control signal VCONT.
Thus, the phase-frequency difference between the reference signal REFCLK and the oscillation-output signal FBCLK transmitted from the voltage-controlled-oscillation circuit 44 is detected. Every time the phase-frequency difference is detected, the oscillation frequency of the oscillation-output signal FBCLK is changed according to the detected phase-frequency difference. Subsequently, the phase and frequency of the reference signal REFCLK are synchronized with those of the oscillation-output signal FBCLK. Hereinafter, the above-described synchronization is often referred to as “to lock”, “locking”, “being locked”, etc.
Various circuits have been proposed, as lock-detection circuits configured to detect whether or not a reference signal and an oscillation-output signal transmitted from a voltage-controlled-oscillation circuit are locked to each other, so as to be used for a PLL circuit such as the above-described PLL circuit 40. For example, a known synchronization-detection circuit is shown in FIG. 5 of Japanese Unexamined Patent Application Publication No. 4-337924. Since the above-described known synchronization-detection circuit requires many analog circuits, the circuit often becomes too alert to the fluctuations and variations of its components. Therefore, it has been difficult to design the above-described known synchronization-detection circuit. For solving the above-described problems, Japanese Unexamined Patent Application Publication No. 4-337924 proposes a synchronization-detection circuit including a logic circuit and a latch circuit, as shown in FIG. 1 of the publication.
Further, Japanese Unexamined Patent Application Publication No. 63-263919 discloses a PLL circuit including a detection unit configured to generate a detection signal when the phase difference between a controlled signal and a reference signal falls within a predetermined range (an acceptable phase-error range) and an acceptable-phase-error-change unit configured to change the predetermined range.
In the synchronization-detection circuit proposed in Japanese Unexamined Patent Application Publication No. 4-337924, the absolute value of the acceptable phase-error range is set, as a steady value. Therefore, it is difficult for the synchronization-detection circuit to determine and detect a locked state and/or an unlocked state at a constant rate due to frequencies and various fluctuations and/or variations.
Further, even though various acceptable phase-error ranges can be set according to frequencies, as is the case with the PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 63-263919, it is often difficult to set an acceptable phase-error range with precision when there are various fluctuations and/or variations.